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VESTEL TIME SHIFT TV
Service Manual


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  • Contains Circuit Diagrams
  • Download
  • PDF Format
  • Complete manual
  • Language: English
Price: $4.99

Description of VESTEL TIME SHIFT TV Service Manual

Complete service manual in digital format (PDF File). Service manuals usually contains circuit diagrams, printed circuit boards, repair tips, wiring diagrams, block diagrams and parts list. Service Manual ( sometimes called Repair Manual ) is used mainly by technicians.

If You just want to know how to use Your tv, video, mp3 player etc. You should look for Owner's Manual. After placing order we'll send You download instructions on Your email address.

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Text excerpt from page 6 (click to view)
synchronisation circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. However, this Ident circuit cannot be made as sensitive as the slower sync Ident circuit (SL) and we use both Ident outputs to obtain a reliable search system. The Ident output is supplied to the tuning system via the I2C -bus. The input of the identification circuit is connected to pin 24, the internal CVBS input. This has the advantage that the Ident circuit can also be made operative when a scrambled signal is received (descrambler connected between the IF video output (pin 16) and pin 24). A second advantage is that the Ident circuit can be used when the IF amplifier is not used The video Ident circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realised with the VIM bit. The IC contains a group delay correction circuit, which can be switched between the BG and a flat group delay response characteristic. This has the advantage that in multi-standard receivers no compromise has to be made for the choice of the SAW filter. Also the sound trap is integrated within the IC .The centre frequency of the trap can be switched via the I 2C -bus. For mono-FM versions it is possible to obtain a demodulated IF video signal which has not passed the sound trap so that an external stereo decoder can be driven. This function is selected by means of the ICO bit (sub-address 28H). The signal is available on pin 27 (audio output pin when ICO = 0). The S/N ratio of the selected video signal can be read via the bits SN1/SN0 in sub-address 03H. 2.2. Video Switches The circuit has an input for the internal CVBS signal and 2 inputs for external CVBS or Y signals. The circuit has only 1 chroma input so that it is not possible to apply 2 separate Y/C inputs. The selection of the various sources is made via the I2C -bus. Two independently switchable outputs are available. The CVBS1O output is identical to the selected signal that is supplied to the internal video processing circuit and which is used as source signal for a teletext decoder. Both CVBS outputs have an amplitude of 2.0 VP -P . The CVBS2O output is used for CVBS-video output. If the Y/C-3 signal is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again. 2.3. Sound Circuit The sound IF amplifier is similar to the vision IF amplifier and has a gain control range of about 66 dB. The AGC circuit is related to the SIF carrier levels (average level of AM or FM carriers) and ensures a constant signal amplitude of the AM demodulator and the QSS mixer. A multiplier realises the single reference QSS mixer. In this multiplier the SIF signal is converted to the intercarrier frequency by mi xing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high -pass filter for attenuation of the residual video signals. With this system a high performance hi -fi stereo sound processing can be achieved. To optimise the performance of the demodulator the offset can be compensated by means of an I 2C -bus setting. The AM sound demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for attenuation of the carrier harmonics. Remark that QSS output pin is 11. 2.4. Synchronisation circuit The sync separator is preceded by a controlled amplifier, which adjusts the sync p ulse amplitude to a fixed level. These pulses are fed to the slicing stage, which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is used to detect whether the line oscillator is synchronised with the incoming signal and can also be used for transmitter identification. This circuit can be made less sensitive by means of the STM bit. This mode can be used during search tuning to avoid that the tuning system will stop at very weak input signals. The first PLL has a very high statically steepness so that the phase of the picture is independent of the line frequency. The horizontal drive signal is generated by an internal VCO, which is running at a freq uency of 25 MHz. This oscillator is stabilised to that frequency by using the 12 MHz frequency of the crystal oscillator as a reference. The time-constant of the first loop can be forced by the I 2C -bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The horizontal output signal is generated by means of a second loop, which compares the phase of the internal oscillator signal with the phase of the incoming flyback pulse. The time -constant of this loop is connected externally and can be used as input for a dynamic horizontal phase correction. To obtain a smooth switch -on and switch-off behaviour of the horizontal output stage the horizontal drive signal is switched -on and off via the soft-start/soft-stop procedure. This function is realised by means of a variation of the TON of the horizontal drive pulse. When the soft-start procedure is completed the horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on during the flyback time. An additional function of the IC is the ‘ low-power start-up’feature. For this function a supply voltage with a value between 3 and 5 V must be available at the start-up pin (required current 5 mA typical). When all sub-address bytes have 2

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